531AA640M000BG【PDF 3/12 页】OSC SMD LLVPECL 640MHZ 3.3V

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Si530/531

Table 2. CLK± Output Frequency Characteristics (Continued)

Parameter

Total Stability

Powerup Time 4

Symbol

t OSC

Test Condition

Temp stability = ±7 ppm

Temp stability = ±20 ppm

Temp stability = ±50 ppm

Min

—

—

—

—

Typ

—

—

—

—

Max

±20

±31.5

±61.5

10

Unit

ppm

ppm

ppm

ms

Notes:

1. See Section 3. "Ordering Information" on page 7 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

3. Selectable parameter specified by part number.

4. Time from powerup or tristate mode to f O .

Table 3. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

LVPECL Output

Option 1

V O

V OD

V SE

mid-level

swing (diff)

swing (single-ended)

V DD – 1.42

1.1

0.55

—

—

—

V DD – 1.25

1.9

0.95

V

V PP

V PP

LVDS Output Option 2

CML Output Option 2

V O

V OD

V O

V OD

mid-level

swing (diff)

2.5/3.3 V option mid-level

1.8 V option mid-level

2.5/3.3 V option swing (diff)

1.8 V option swing (diff)

1.125

0.5

—

—

1.10

0.35

1.20

0.7

V DD – 1.30

V DD – 0.36

1.50

0.425

1.275

0.9

—

—

1.90

0.50

V

V PP

V

V

V PP

V PP

CMOS Output Option

3

V OH

V OL

I OH = 32 mA

I OL = 32 mA

0.8 x V DD

—

—

—

V DD

0.4

V

V

Rise/Fall time (20/80%)

t R, t F

LVPECL/LVDS/CML

CMOS with C L = 15 pF

—

—

—

1

350

—

ps

ns

Symmetry (duty cycle)

SYM

LVPECL:

V DD – 1.3 V

(diff)

LVDS:

1.25 V (diff)

45

—

55

%

Notes:

1. 50 ? to V DD – 2.0 V.

2. R term = 100 ? (differential).

3. C L = 15 pF

CMOS:

V DD /2

Rev. 1.4

3

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